Hardware simulation: a flexible approach to verification and performance evaluation of communication protocols

摘要

Communication protocols can be modeled as finite state machines, a formalism commonly used in digital circuit design. Sophisticated and efficient simulation techniques have been developed to help integrated circuit designers. In this paper, we propose an approach to the verification and performance evaluation of communication protocols and, in general, of entire computer networks based on such techniques. Preliminary results seem to indicate the feasibility of the method.