Implementation and Analysis of Low Power Consumption Full Swing GDI Full Adders

摘要

Power efficiency of any design can be obtained in terms of PDP. The approach used to design any system defines the performance of system. Here, Gate Diffusion Input (GDI) design techniques as well as CMOS design techniques are used for designing full adder circuits. Full swing GDI technique is utilized to reduce power consumption and delay. Full swing GDI technique gives better speed of operation as compared to CMOS technique. While keeping these parameters at best GDI maintains low complexity of design. Full adder circuits are designed using 180 nm technology node in Cadence Virtuoso with supply voltage of 1.8 V.