Multi-input multiplexers and selectors as basic shifter blocks in arithmetic devices operating in floating point: comparative analysis

摘要

In case of the Field Programmable Gate Array implementation of arithmetic devices operating in floating point, the implementation of shifters is associated with some challenges. This work compares two approaches to the formation of basic shifter blocks: as selectors using carry chains and as multi-input multiplexers. Both approaches use exclusively a FPGA programmable logic. The work shows that basic blocks as multiplexers require more than twice fewer FPGA logic slices and are notable for 10-20% better performance when compared to those based on selectors.