ISFET Array Readout System with Integrated 12 bit A/D Conversion for Lab-on-Chip Applications

摘要

This work presents a current-mode readout frontend for a 128 × 64 array of ISFETs integrated in 180 nm 1P6M CMOS technology. The most relevant ISFET systems have not been implemented using single device configurations, instead, ISFETs in an array configuration has been used. The proposed front-end architecture linearly digitizes the output current of the ISFET array through a current conveyor, a transimpedance amplifier, and a 12 bit SAR ADC. A slave I2C digital circuit controls the array ISFET selection decoders and serializes the ADC output. Linearity of R^{2 = 99.94%, current consumption of 450 µA, and a low-frequency ENOB of 11.24 bit were achieved by post-layout simulation. The implemented chip occupies 0.52 mm2. Prototypes just arrived from the foundry and experimental measures will be performed soon.}