Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters

摘要

We propose a virtually nonvolatile retention flip-flop (VNR-FF) applicable to energy-efficient power-gating systems, which is suitable for SoCs used in smart mobile devices. The proposed VNR-FF can retain its data using ultralow shutdown-state voltage induced by power-switches in logic domains. The VNR-FF is configured with dual-mode inverters that act as a Schmitt trigger inverter during ultralow-voltage retention mode and as a conventional (or boosted) inverter during ordinary-voltage normal operation mode. Design methodologies of VNR-FFs are developed from the viewpoints of their leakage and speed performances. Energy, speed, and retention performances of VNR-FFs are computationally analyzed.