SQNR improvement in fixed-point FFT architecture

摘要

In Digital Signal Processing (DSP), Fast Fourier Transform (FFT) algorithm and its hardware implementation play a significant role. To implement FFT in hardware, fixed point arithmetic is preferred as it is simple to execute and also saves area and power. The finite bit representation of signals and coefficients in fixed point result in quantization error which degrades FFT performance mainly Signal to Quantization Noise Ratio (SQNR). In this paper, SQNR improvement in fixed-point FFT is achieved by modifying Radix-2 Decimation In Time (DIT) conventional butterfly structure.