root i ( i) arithmetic radix-8 fixed-point FFT logic circuit characterized by a retention of

摘要

PROBLEM TO BE SOLVED: To reduce the rounding error of a high speed Fourier transformation (FFT) arithmetic operation.;SOLUTION: Data appearing as an irrational number (√, square root) among rotation factors on a complex plane included in a butterfly arithmetic operation (8p) are not intentionally calculated, but preserved in a memory installed in one stage among a plurality of stages of an FFT integrated into a pipe line in multi-stages, and when the data reappear in the subsequent stage, an arithmetic operation to multiply two rotation factors is performed. Thus, it is possible to eliminate any rounding error during the butterfly arithmetic operation (8p) of a radix 8(radix-8). Furthermore, it is possible to apply this invention to cover more stages by the butterfly arithmetic operation of a radix 2(radix-s) or a radix (radix-4).;COPYRIGHT: (C)2012,JPO&INPIT