A 1.2V 10 bits 100-MS/s analog-to-digital converter with a 8-stage pipeline and a 2 bits flash ADC

摘要

This paper presents a 10bits 100-MS/s low-voltage pipelined analog-to-digital converter (ADC), which consists of 8-stage-pipelined low resolution ADCs and a 2-bit flash ADC. Several critical technologies are adopted to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, folded-cascode gain-boosted amplifiers. The ADC is designed in a UMC 90nm CMOS technology with a 1.2V supply voltage.