Low power hardware design for montgomery modular multiplication

摘要

This paper describes the design and implementation of low power modular multiplier of RSA and balances its area and speed. By improving Montgomery modular multiplication algorithm, optimizing critical path and using several low power methods, this paper achieves low power as well as high speed performance. The design is implemented using SMIC 0.13um CMOS process, the average power consumption is 106uW at 13.56MHZ when executing 1024-bit operations, the area is about 0.17mm2 and the time to finish modular multiplication are 1412 clock cycles, such excellent property make it suitable for RSA operation.