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Simulation and Analysis of DS-SS Anti-jamming Performance Based on VHDL

机译:基于VHDL的DS-SS抗干扰性能的仿真与分析

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Arming at the difficulty of traditional simulation method to achieve analysis of DD-SS Anti-jam capability in engineering area and the implementation complexity using pure hardware, the paper introduces a simulation scheme based on VHDL. Two different spread spectrum gain systems are designed. The noise is recommended to the spread spectrum signal which characterizes manufacture under various interference. Search and acquisition by sequence phase method is adopted to complete the synchronization and to accomplish correlation despreading. Through increasing gradually noise in two spreading gain systems respectively, anti-jam performance of the system is analysised under different interference environment. Simulation result shows that increasing spreading gain can improve anti-jam capability. When spread spectrum gain is 127, the system can despread correctly by 26% bit error rate of received spread spectrum signal. If Spread spectrum gain increases 3 dB, the system despreads with zero error code even by 38% bit error rate of received signal. The simulation method and the conclusion have some reference value for the actual application.
机译:武装难以实现传统仿真方法的难度,实现工程区DD-SS抗堵塞能力的分析和使用纯硬件实现复杂性,介绍了基于VHDL的仿真方案。设计了两个不同的扩频增益系统。建议噪声到扩频信号,其在各种干扰下的制造表征。采用序列阶段方法搜索和获取来完成同步并完成相关解扩。通过分别增加两个扩展增益系统的逐渐噪声,在不同的干扰环境下分析系统的抗卡纸性能。仿真结果表明,增加的扩展增益可以提高抗卡纸能力。当扩频增益为127时,系统可以正确地解析26%的接收扩频信号的误码率。如果扩频增益增加3 dB,则系统向零误差码扩展为零误差码,即使接收信号的38%误码率也是如此。仿真方法和结论具有实际应用的一些参考值。

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