Low-cost router microarchitecture based on dimension-switch for fault-tolerance in 2D-Mesh NoC

摘要

Implementing fault-tolerance in Network-on-Chips (NoC) with low area-cost and low latency is a great challenge recently. In this paper we propose a low area-cost and low-latency router for Fault-Tolerance in 2D-Mesh NoC. Compared to generic VC (Virtual Channel) router, we depart a single switch into two small ones for each dimension and abandoning virtual-channel mechanism so as to enormously reduce the area-cost. By introducing a dimension-switch data packets can transfer between dimensions and routing flexibility is also supported. And the number of buffers in dimension switch can be adjusted according to different routing algorithms. Also, the fault model is proposed in a small granularity. A reconfigurable fault-tolerant solution is applied to a 5-ary 2-cube NoC based on this router to test the performance. Finally, the simulation results show that with low-latency the area cost of the proposed router is reduced to extremely low compared with that of the generic VC router with a single switch and virtual-channel mechanism.