Accurate timing information of circuits is essential for high quality designs. This paper presents a symbolic event propagation based method to determine the critical delay of digital circuits. The proposed approach considers the effect of glitches, multiple transitions and simultaneous switching on the critical delay. Our method identifies and eliminates both combinational and sequential false paths. We also consider triggering of traditional combinational false paths due to multiple transitions. The mathematical formulation makes no assumption about the start state of the finite state machine extracted from the sequential circuit. Few approximate methods have been proposed to determine the upper bound of the critical delay. A complete BDD based implementation has been made. Results on ISCAS89 benchmark circuits are presented.
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