Toward on-chip JIT synthesis on Xilinx VirtexII-Pro FPGAs

摘要

Xilinx VirtexII Pro FPGAs support dynamic reconfiguration. To benefit from this functionality, Xilinx proposes a modular and differential development flow, which consists in precompiling all possible configurations and switching from one to another in real time. The pre-compilation process is too slow and static. Xilinx also supplies JBits, but this tool does not support the VirtexII Pro FPGA and later devices. We aim to dynamically produce digital circuits. Unfortunately, since Xilinx does not entirely document the format of the FPGA bitstreams, it is in principle impossible to produce bitstreams without using their tools. This paper presents the methodology we have used to determine the Xilinx bitstream format in order to quickly produce valid configurations on the fly using only our tools. Our synthesis approach translates a simple expression language into a dataflow graph of predefined tiles which are placed and interconnected using the bitstream format information we gathered.