A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses

摘要

Transaction Level Modeling (TLM) and efficient system level simulation have become invaluable tools for analysis and design of state of the art embedded systems. Abstraction level of the models used in simulation depends on the use case and there is a strong trade off between simulation speed and accuracy. In traditional TLM, the abstraction level of the models is fixed during simulation. Often, except for some intervals during simulation, the models are too accurate for the simulation scenario, negatively affecting simulation speed. In this paper we propose an adaptive TLM for pipelined buses with an accuracy that dynamically adapts to the simulation scenario. The proposed model accurately models latency, preemption and data transfer timings. Considering complex timing properties of pipelined buses this level of accuracy is only available in much slower, cycle accurate models. We have developed an adaptive model of the AMBA AHB protocol in SystemC based on the OSCI TLM 2 standard. Comparison of our model with existing non-adaptive models and analysis with data traffic in real world embedded systems clearly show the improvement in performance without the loss of accuracy.