Design and implementation of ADPLL for Digital communication applications

摘要

ADPLL has a great role in Digital Communication. This paper presents the design and implementation of ADPLL for digital communication applications. All the blocks of ADPLL are designed as digital. The center frequency of the ADPLL is 200 kHz. The lock range of ADPLL is from 188 kHz to 212 kHz. Designed ADPLL is used for Digital Communication Applications like Amplitude Shift Keying (ASK), Phase Shift Keying (PSK), Quadrature Phase Shift Keying (QPSK), Frequency Shift Keying (FSK) and Quadrature Amplitude Modulation (QAM). Digital blocks are designed using VHDL. Xilinx ISE 14.2 is used for simulating our design.