Multi-Processor Systems-on-a-Chip (MPSoC) based on time-triggered on-chip networks facilitate fault isolation, temporal predictability and mixed-criticality integration. In mixed-criticality systems, a shared memory can be realized on top of time-triggered message passing to effectively support heterogeneous applications with different interaction paradigms. This paper presents a simulation environment of such an MPSoC combining message-based and shared-memory interactions. We present SystemC simulation building blocks for the application cores, network interfaces and the time-triggered network-on-a-chip. The behavior of the application cores is described by Transaction-Level Modeling (TLM). We generate traces from the application software or from benchmarks, which serve as input for the access to the network interfaces. The simulation framework is evaluated using a realistic case study based on SPLASH-2 and PARSEC application benchmarks. The simulation framework is essential for early validation and design space exploration of mixed-criticality systems. The high abstraction level provided by TLM and traces ensures high simulation speeds.
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