The research and implementation of test access mechanism based on SoCs

摘要

Based on the SoC d695 in ITC'02 benchmark circuits, the hierarchical structure model of SoCs testing system chips is established. Using the hardware and software co-design ideas design and optimization the test structure model, appropriate multi-level test access mechanism, parallel test unit of SoCs wrapper design and SoCs multi-level test access mechanism (TAM) are designed, grouped SoCs flexible allocation of bandwidth TAM testing strategy is proposed using macro-control module to achieve testing schedule control. The SoCs hierarchical test structures divide and conquer, parallel testing, increased the flexibility of the test to improve test efficiency and saved test time, which increasingly complex hierarchical SoCs testable realization has great practical significance and optimization.