Research on Verification and Implementation of RTL-based VHDL Simulator

摘要

VHDL simulator based on Register Transfer Level (RTL) is implemented and verified, named RVS. Firstly, we give the implementation of RVS. Secondly, we design the micro program SAP-CPU and logic SAP-CPU based on VHDL language, which includes the format of control instruction, instruction set, addressing method, test program and the architecture of logic SAP-CPU and micro program SAP-CPU. Finally, the experiment and analysis show that the simulator of RVS perform well and produce encouraging solutions correctly on two SAP-CPU designs controlled by combinational logic and micro-program.