Numerical Study on Gate-All-Around Tunneling FET with SiO2 Core and Si Shell Structure

摘要

This work presents a gate-all-around tunneling FET based on SiO2 core and Si shell structure (GAA-SOI-TFET) and demonstrates its performance characteristics via the numerical simulation method. The 3-D T-CAD numerical simulations demonstrate that this new device has steep subthreshold swing (<60mV/dec), suppressed drain-induced barrier lowering, and enhanced Ion/Ioff ratio up to 10~9 orders of magnitude. It is worth noting that Ion begins to increase when SiO2 core radius exceeds a specified valu (～4nm) while influnce of gate oxide thickness on the device performance being an important factor.