Ⅲ-Ⅴ/Ge CMOS Device Technologies for High Performance Logic Applications

摘要

One of the ultimate CMOS structures can be the combination of Ⅲ-Ⅴ nMOSFETs and Ge pMOSFETs, because of high mobility and low effective mass. In order to realize Ⅲ-Ⅴ/Ge CMOS, common gate stack and source/drain (S/D) formation technologies are important. Here, an atomic layer deposition (ALD) Al_2O_3 gate insulator and Ta metal gate were used for common gate stacks for InGaAs and Ge. This is because ALD Al_2O_3 can provide good MOS interfaces with InGaAs as well as Ge with post electron cyclotron resonance (ECR) plasma oxidation. Also, self-aligned Ni-Ge and Ni-InGaAs, which can be formed simultaneously for InGaAs nMOSFETs and Ge pMOSFETs, were used as the metal S/D regions. By utilizing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on the same wafer. In order to realize the integration of Ⅲ-Ⅴ/Ge MOSFETs, we have bonded Ⅲ-Ⅴ substrates with Ge substrates. We have found good transistor operation in both devices. High I_(on)/I_(off) ratio of ～10~6 was obtained for InGaAs-OI nMOSFETs. The high electron and hole mobility of 1800 and 260 cm~2/Vs and the mobility enhancement against Si of 3.5 × and 2.3 × have been demonstrated for InGaAs-OI nMOSFETs and Ge pMOSFETs, respectively.