ROBUST LOW-POWER CMOS PRECHARGE LOGIC

摘要

In this paper we improve the Ultra Low-Voltage gate by including a keeper transistor at the floating-gate to make the gate more static. Thus, the refresh overhead is excluded, in addition the power consumption in evaluation period is significant lower. We also evaluate the gates behaviour for the effect of delayed input signal. All results are obtained by simulation in Cadence for a 90 nm process parameters.