Due to the ever increasing sensitivity of CMOS circuits to soft errors, reliability is still one of the main research topics in the domain of integrated systems. Recent research has shown, that by tolerating a certain number of errors within the circuit, to an extend, so that they get barely noticed by the user, the circuit could gain substantially in terms of performance, power or area. In order to enable such an approach, a comprehensive analysis of the circuit has to be done. We developed an FPGA-based probability-aware fault emulator supporting this analysis. The demo will show that reliability constraints can be relaxed inside a circuit without a noticeable effect for the end-user, when carefully investigating where the constraints can be relaxed and to what extend. In this demo we will show, how this investigation can be done fast and accurate using our emulation framework.
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