The common method of implementing a HDLC controller is either using an ASIC device or designing it with software. It is easy to implement a HDLC controller with an ASIC device, but it is hard to modify it. The software method introduces a flexible way, but it will occupy a huge amount of CPU resource, and the timing parameters are hard to ensure. Designing HDLC controller with FPGA can take advantage of both speed and flexibility, furthermore, with the programmable ability of FPGA, more than one channel can be implemented in a single FPGA. This paper introduces a HDLC controller design base on Altera's Cyclone III FPGA and Quartus II developing environment. The controller contains four HDLC channels and an interface for PC104 bus. Except the basic HDLC protocol, more functions are added into the controller, such as alterable flag sequence, built-in timer and so on. The design has been fully tested, and has been used in a communication production successfully.
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机译：实现HDLC控制器的常用方法使用ASIC设备或使用软件设计。使用ASIC设备易于实现HDLC控制器，但很难修改它。该软件方法引入了灵活的方式，但它将占用大量的CPU资源，并且定时参数很难确保。使用FPGA设计HDLC控制器可以利用速度和灵活性，此外，通过FPGA的可编程能力，可以在单个FPGA中实现多个通道。本文介绍了Altera Cyclone III FPGA和Quartus II开发环境的HDLC控制器设计基础。控制器包含四个HDLC通道和PC104总线的接口。除基本的HDLC协议外，还将更多功能添加到控制器中，例如可变的标志序列，内置定时器等。该设计已完全测试，已成功地用于通信生产。
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