This paper presents different strategies to improve the energy efficiency of nanoscaled Si based devices. Processing and device characteristics of nanowire (NW), Ge quantum dot (QD) metal oxide semiconductor field-effect transistors (MOSFETs) as well as tunnel FETs are discussed. A comparison of NW array devices containing uniaxially strained wires fabricated with SiO_2/poly and HfO_2/TiN gate stack is presented. The high uniaxial strain along the NWs reduces the band gap energy by approximately 140 meV and enhances the electron mobility. The hole mobility may be enhanced by proper choice of NWs orientation. Ideal inverse subthreshold slopes of n- and p-channel devices of 60 mV/dec at room temperature and I_(on)/_(off ratios up to 10~(10) were obtained. Based on same 3D architecture Si and SiGe Tunnel FET are fabricated. For TFETs relatively high on-currents and good slopes <80 mV/dec were obtained. The typical ambipolar behavior of TFETs could be greatly suppressed by the use of a SiGe source tunneling junction.
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机译：本文介绍了提高基于纳米SI器件的能效的不同策略。讨论了纳米线（NW），Ge量子点（QD）金属氧化物半导体场效应晶体管（MOSFET）以及隧道FET的处理和装置特性。呈现了NW阵列装置，其包含由SiO_2 / Poly和HFO_2 / TIN栅极堆叠制造的单轴应变丝的装置。沿着NWS的高单轴应变将带隙能量减小约140mEV并增强电子迁移率。 The hole mobility may be enhanced by proper choice of NWs orientation.理想的逆亚阈值在室温下60 mV / DEC的N和P沟道器件的斜坡斜坡和I_（ON）/ _（最多10〜（10）的截止比率。基于同一3D架构SI和SIGE隧道FET是制造的。对于TFET，获得了相对高的电流和良好的斜率<80 mV / DED。通过使用SiGe源隧穿接合点可以大大抑制TFET的典型的Ambolar行为。
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