Optimization design of reed-solomon decoder based on FPGA

摘要

In order to improve anti-jamming capability, the tactical data link uses RS (31, 15) coding/decoding in data transmission. In this paper, a RS (31, 15) hardware decoder base on RIBM algorithm is introduced, and this decoder is designed and implemented by pipeline algorithm. To make up the key equation module's deficient in the whole pipeline, a modified RIBM algorithm is proposed, and the logic resource is also reduced. Besides, the Chien search module and the Forney module are assembled and optimized, further simplifying the structure of the decoder.