Comprehensive On-Chip Traffic Generator Model for SoC Design and Synthesis

摘要

On-Chip traffic Modeling is a new research topic that came along with Network on Chip (NoC) design. On-chip traffic varies in rate and nature depending on the running application and the System on Chip components. Different traffic models have been proposed as an attempt to capture the various transactions that occur inside the NoC, which connects different Intellectual Properties (IPs) on the same chip. In this research paper, recent traffic modeling paradigms will be reviewed and discussed. These models have been developed into traffic generator entities to emulate the traffic patterns on chip. However, none of these models (and hence traffic generators) completely capture the behavior of different applications and the interactions between different IPs components on chip, which can alter the traffic state and rate. In this paper, we will propose a comprehensive and flexible model that is based on Discrete EVent System Specification formalisms (DEVS) for modeling and simulation. Our model could be implemented as a traffic generator that has three internal functions, and input and output ports for the interactions with other IPs components such as caches, DSP units, etc.