This paper presents the outline design of a CMOS stimulator ASIC to be embedded in implantable electrodes. The stimulator is designed to drive four tripolar output channels on an electrode “book” with independent settings on the ratio of anodic currents for each individual channel. Power and data are sent to the ASIC via five wires from a central hub unit. This configuration significantly reduces the cable count for multichannel stimulation applications. The stimulator supports a quiescent mode in which only sub-μA current is drawn from the supply. The ASIC was designed in a 0.6-μm HV CMOS process and post-layout simulation results are presented.
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