Variability aware yield optimal sizing of analog circuits using SVM-genetic approach

摘要

During analog circuit synthesis in nanometer technology, process variability analysis is mandatory during design space exploration. This would ensure that the circuit will function as per specifications after fabrication even with impact of statistical variations in nanometer regimes. The methodology necessitates the evaluation of performance metrics of an analog circuit for different sizing instances of the transistors. Circuit simulation for performance evaluation is very time consuming and is seldom a choice while sizing a circuit for a chosen topology. The complexity of sizing methodology increases with the need to consider effects of variations in process and environment parameters. We employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits during sizing and yield optimization loops. The objective to improve evaluation efficiency has been the motivation behind efforts to develop performance macromodels, which should be as accurate as SPICE and at the same time have shorter evaluation time for use in the sizing of analog circuits, where they are used as substitutes for full circuit simulation during circuit sizing (synthesis). Process variability aware SVM macromodels are used in the multiobjective multivariate sizing method which is also yield optimal. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. Its application as process variability analysis tool is illustrated on two stage op amp and a voltage controlled oscillator using 90 nm BSIM4 models of transistors.