For the LHC a VME card has been developed that contains all functionalities for transverse damping, diagnostics and controlled bunch by bunch excitation. It receives the normalized bunch by bunch position from two pick-ups via Gigabit Serial Links (SERDES). A Stratix II FPGA is responsible for resynchronising the two data streams to the bunch-synchronous clock domain (40.08 MHz) and then applying all the digital signal processing: In addition to the classic functionalities (gain balance, rejection of closed orbit, pick-up combinations, one-turn delay) it contains 3-turn Hilbert filters for phase adjustment with a single pickup scheme, a phase equalizer to correct for the non-linear phase response of the power amplifier and an interpolator to double the processing frequency followed by a low-pass filter to precisely control the bandwidth. Using two clock domains in the FPGA the phase of the feedback loop can be adjusted with a resolution of 10 ps. Built-in diagnostic memory (observation and post-mortem) and excitation memory for setting-up are also included. The card receives functions to continuously adjust its parameters as required during injection, ramping and physics.
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机译：对于LHC，已经开发了VME卡，其中包含横向阻尼，诊断和受控束的所有功能。它通过千兆位串行链路（SERDES）从两个接送器中接收归一化束。 Stratix II FPGA负责将两个数据流重新同步到束同步时钟域（40.08 MHz），然后应用所有数字信号处理：除了经典功能外（增益平衡，拒绝闭合轨道，接送组合，一圈延迟）它包含3圈Hilbert滤波器，用于使用单个拾取方案进行相位调整，一个相位均衡器，用于校正功率放大器的非线性相位响应和插值器，以加倍处理频率，然后是a低通滤波器精确控制带宽。使用FPGA中的两个时钟域可以通过10 p分辨率调整反馈回路的相位。还包括内置诊断存储器（观察和验尸）和用于设置的激励存储器。卡接收功能以在注射，斜坡和物理学期间连续调整其参数。
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