Structural and Electrical Analysis of Thin Interface Control Layers of MgO or Al_2O_3 Deposited by Atomic Layer Deposition and Incorporated at the high-A/III-V Interface of MO_2/In_xGa_(1-x)As (M = HfZr, x = 00.53) Gate Stacks

摘要

The control of the high-MII-V interface during integration of high dielectric constant (k) gate oxides on III-V channels for future generations of metal-oxide-semiconductor (MOS) devices is a significant technological challenge. The chemistry involved in the creation of the high-MII-V interface is more complex than the similar SiO_2/Si and high-k/Si interfacial chemistries (1) due to the number of elements involved in the III-V substrates relative to a Si substrate. This is complicated by competition between the III-V native oxides themselves (2). If high-k materials are to be successfully integrated as gate oxide materials in conjunction with III-V substrates, solutions must be found to improve the interface quality.