Parallel Matrix Algorithm Autotuner on Multi-core Architecture

摘要

This paper develops a performance autotuner of the parallel sparse matrix multiplication algorithm. This autotuner can utilize the cache characters of multicore computers. It can optimize the value of performance parameters in multicore and achieve the better performance of parallel matrix multiplication algorithm. This paper proposes a parallel matrix multiplication algorithm by Using the CSR compression and cache blocking technology. The cache blocking parameters are optimized to get the better performance. From the matrix experiments, we can consult that the autotuner system can achieve the sparse matrix multiplication algorithm better performance on the multicore hardware.