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Lagrangian relaxation based register placement for high-performance circuits

机译:拉格朗日放松基于高性能电路的寄存器放置

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To achieve low-skew clock distribution, clock tree synthesis (CTS) for local clock optimization is used so far. Challenged by the increasing design complexity and performance demand, a new strategy for local clock optimization is used along with register placement for high-performance circuits. Special local clock distribution is used and registers are legalized to fit required skew. In this paper, we study the register placement problem and formulate it as a minimum weighted maximum independent set problem on a weighted conflict graph. Then, we propose a novel Lagrangian relaxation based algorithm. By relaxing the overlap conflict constraints, the problem is transformed into a minimum weighted bipartite matching problem. Experiments show that our method can efficiently place all registers without overlaps with minimized total register movement.
机译:为了实现低歪斜的时钟分布,到目前为止使用局部时钟优化的时钟树合成(CTS)。由于设计复杂性和性能需求的增加,局部时钟优化的新策略以及用于高性能电路的寄存器展示率。使用特殊的本地时钟分配,并且寄存器合法化以适应所需的偏斜。在本文中,我们研究了寄存器放置问题并将其作为加权冲突图中的最小加权最大独立集合问题。然后,我们提出了一种基于Lagrangian弛豫的新颖的基于Lagrangian Sourtation。通过放松重叠冲突约束,问题转换为最小加权二分匹配问题。实验表明,我们的方法可以有效地将所有寄存器放置,而不会与最小化的总寄存器移动重叠。

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