In this paper, novel FinFET device structures with its bodies been connected together have been for the first time proposed by three-dimensional (3-D) simulation. The short-channel characteristics of threshold voltage (V_(TH)), drain induced barrier lowering (DIBL), and on-off ratio current performance have been examined and explained in this paper. Also, the novel structures show the desired characteristic performance when using different kind of wafer, such as bulk wafer and silicon on insulator (SOI) wafer. Our proposed devices can not only lower the V_(TH), but also reduce the leakage current due to its active body been connected. In addition, it can also help us to develop a new low cost fabrication technology for the future technology node.
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