Efficient Scratchpad Memory Management Based on Multi-Thread for MPSoC Architecture

摘要

Scratchpad memory (SPM) is software-controlled on-chip memory with shorter access time and lower power consumption compared with cache. SPM is used increasingly widespread to meet the strict requirements on performance, power consumption and design cost of the embedded systems. This paper presents an efficient SPM management based on multithread for multiprocessor system on chip (MPSoC) architecture, which is the popular in embedded processors. The proposed mechanism is composed of: (1) processor core groups; (2) SPM primitives; (3) SPM based multi-thread scheduling. The experimental results show that the proposed mechanism can improve the performance of the system with lower power consumption.