Analog Design Retargeting by Design Knowledge Reuse and Circuit Synthesis

摘要

In this paper, we present an empirical method for efficient analog design retargeting by combining design knowledge reuse and circuit synthesis. The method first decomposes the source system into circuit blocks and extracts the performance parameter specifications of each circuit block. Then, it scales each circuit block and defines a design space in the target technology. Subsequently, each circuit block is synthesized. Our assumption is that if the synthesized circuit blocks retain the same set of performance specifications, then the overall system after retargeting would have the same performance specification as the source system. We experiment the method on a fourth order continuous-time Delta-Sigma modulator.