A Low Power 90-nm CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling (DVFS) and Fast Motion Estimation Algorithm

摘要

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage (V_(D)) and the optimum clock frequency (f_(c)) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to 29.1 (mu)W, which was only 3percent that of a conventional ME processor.