首页> 外文会议>International Symposium on Circuits and Systems >A Capacitor-Less Low-Dropout Regulator for SoC With Bi-Directional Asymmetric Buffer
【24h】

A Capacitor-Less Low-Dropout Regulator for SoC With Bi-Directional Asymmetric Buffer

机译:具有双向非对称缓冲器的SOC的电容器较少的低压丢失调节器

获取原文

摘要

A 1.0-V, 50-mA capacitor-less low-dropout (LDO) voltage regulator with 100pF internal output capacitor for SoC applications is presented. The proposed LDO makes use of a bi-directional asymmetric buffer (BDAB), which provides a signal inversion feedback path and a signal non-inversion feedforward path with different magnitudes at the same time. The feedback path can perform frequency compensation and transient enhancement, while the feedforward path can improve the stability and increase the unit-gain frequency (UGF) by removing right-half-plane (RHP) zero. Simulation results show that the LDO has robust stability, high UGF (up to 1.7-MHz even at no-load), and excellent transient response performance. The overshoot and undershoot of the output voltages are less than 100-mV when the load step changes between 0 and 50-mA in 1-(mu)s, the settling time is 2-(mu)s, while the dropout voltage is 100-mV at full-load current.
机译:提出了一个1.0-V,50-mA电容器的低丢失(LDO)电压稳压器,具有100PF内部输出电容器的SOC应用。所提出的LDO利用双向不对称缓冲器(BDAB),其提供信号反转反馈路径和信号不反转前馈路径,同时具有不同的大小。反馈路径可以执行频率补偿和瞬态增强,而前馈路径可以通过移除右半平面(RHP)零来提高稳定性并增加单位增益频率(UGF)。仿真结果表明,LDO具有稳定的稳定性,高UGF(即使在空载中最多1.7-MHz),以及出色的瞬态响应性能。当负载步骤在1-(mu)S中的负载步骤在0到50-mA之间变化时,输出电压的过冲和下冲小于100-mV,稳定时间是2-(mu)S,而辍学电压为100全负载电流中的-mv。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号