MODELING 32 V ASYMMETRIC LDMOS USING AURORA AND HSPICE LEVEL 66 FOR 180NM TECHNOLOGY

摘要

In this work, the modeling strategy of 32V asymmetric High Voltage MOSFETs fabricated in 180nm High Voltage CMOS process technology using Aurora and Hspice level 66 is presented. The model is validated on the measured characteristics of asymmetric HV MOSFET and implemented on commercial circuit simulator HSPICE. The model shows excellent DC IV characteristics and good behavior for capacitances. The model also exhibits excellent scalability with transistor width and length where the model accuracy of the extracted VTH and IDSAT are within 0 to 5% at T=25°C.