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Research and Implementation of Embedded Layout Accelerator Based on Multi-Cores System

机译:基于多核系统的嵌入式布局加速器的研究与实现

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In this paper, our work is to frame multi-core processors systems which complete  parsing PDF, and in order to parse quickly, we also design hardware accelerator for the graphics rendering engine which are time-consuming most. The final implementation of the system has been tested using a Xilinx University Program Virtex-II Pro Development Board, which features a Virtex-II Pro XC2VP30 Speed Grade -7 FPGA.
机译:在本文中,我们的作品是框架框架的多核处理器系统,该系统完全解析PDF,并迅速解析,我们还为耗时的图形渲染引擎设计了硬件加速器,这些加速器最耗时。该系统的最终实施已经使用了Xilinx Universit Program Virtex-II Pro开发板进行了测试,该计划具有Virtex-II Pro XC2VP30速度级-7 FPGA。

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