In this paper, we present a Multilevel Hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15% and 10% on average for MCNC benchmark designs compared with the start-of-art vpr tool.
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