In this work, we present architecture for real-time implementation of INTRA 4X4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4×4 is composed by intra prediction 4×4, integer transform 4×4, quantization 4×4, inverse integer transform 4×4, inverse quantization 4×4. This hardware is designed to be used as part of a complete H.264 video coding system for video conference applications. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The proposed architecture is implemented in VHDL. The VHDL code is verified to work at 160 MHz in an ALTERA Stratix II FPGA. This architecture can process one macroblock (MB) for 432 clock cycles.
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机译：在这项工作中，我们呈现了H.264 / AVC基线配置文件视频编码标准中使用的4x4算法的实时实现的架构。帧内4×4由帧内预测4×4，整数变换4×4，量化4×4，逆整数变换4×4，逆量化4×4。该硬件旨在作为用于视频会议应用程序的完整H.264视频编码系统的一部分。该架构提出了最小延迟，最大吞吐量，充分利用硬件资源，并结合流水线和并行处理技术。所提出的架构是在VHDL中实现的。 VHDL代码验证以在Altera Stratix II FPGA中以160 MHz工作。此架构可以处理一个宏块（MB）432个时钟周期。
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