A 3rd 3bit Sigma-Delta Modulator with Data Weighted Averaging for Reducing Delay Time

摘要

This paper presents A 3rd order sigma-delta modulator with minimize a feedback delay time of DWA (Data Weighted Averaging). The 3rd order sigma-delta modulator go through Matlab modeling for defining stable coeffietients of the integrator and limiting of non-ideality charateristics. The used fully differential switched capacitor integrator, comparator and DWA are designed transistor level by considering non-idealities. The modulator with proposed DWA structure improve timing margin about 23%. The designed sigma delta modulator with proposed DWA performs maximum SNR (Signal to Noise Ratio) of 79 dB, DR (Dynamic Range) of 78 dB and power consumption of 120mW in sampling frequency of 82.8 MHz.