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NOISE PERFORMANCE OF FRACTIONAL-ORDER PHASE-LOCKED LOOP

机译:分数阶段锁相环的噪声性能

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An analog fractional-order phase-locked loop (FOPLL) is investigated under noisy conditions. The FOPLL using fractional voltage-controlled oscillator (FVCO) and a fractional loop filter (FLF) outperforms its integer-order counterpart for both noisy and noiseless signals. Reducing the loop fractional orders increases both the locking and capturing ranges, and the bandwidth of the FOPLL, which substantially improves the loop transient behavior. However, an increase in the FOPLL bandwidth makes it susceptible to noisy signals. Hence, a compromise has to be made between the loop gain and the loop fractional order to alleviate the effect of noisy signals. The main points of this work are illustrated via simple numerical example.
机译:在嘈杂的条件下研究了模拟分数阶阶段锁定环(FOPLL)。使用分数电压控制振荡器(FVCO)和分数回路滤波器(FLF)的FOPLL优于其整数顺序对应物,用于噪声和无噪声信号。减少环形分数令增加锁定和捕获范围,以及FOPLL的带宽,基本上提高了环路瞬态行为。然而,FOPLL带宽的增加使其变得易受噪声信号。因此,必须在循环增益和环形分数顺序之间进行折衷以减轻噪声信号的效果。通过简单的数字示例说明了这项工作的要点。

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