There are ever increasing challenges when developing test fixtures for high-speed applications using automated test equipment (ATE). This is due to the many variables and considerations that must go into developing characterization test fixtures for I/O cells in the 5 to 10 Gbps range. The purpose of these fixtures is to provide the best possible signal integrity of multi-gigabit data signals between the ATE and the device under test (DUT) [1,2]. One of the variables and considerations that needs to be controlled is the correct choice of dielectric material. Although there is a significant amount of work on dielectric loss for microwave applications, high-speed digital applications have different requirements given the broad frequency bandwidth of digital data patterns, as well as the high density of the I/O interconnects. Modern integrated circuits might have hundreds of differential high speed I/O cells requiring complex multilayer printed circuit boards (PCB) composed of different dielectric materials to be utilized for the test fixtures. There is already a significant amount of work from the industry in evaluating dielectric materials for PCB manufacturing [3,4]. In this article we will show that if appropriate care is taken on minimizing the other PCB loss factors like resistive loss and skin effect loss [2], the dielectric loss for applications in the 10Gb/s range can be at an acceptable level even when not using the lowest loss dielectric materials. The additional losses from a higher loss material can be compensated through equalization techniques [5]. Multi-layer test fixtures with layer counts typically above 20 are required for addressing current high-speed digital IC's. This restricts the choice of suitable dielectric materials, since manufacturing difficulty and yield become key factors. The highest performance low loss dielectric materials like Teflon do not laminate well for creating multiple stripline routing layers and cannot be used effectively in these high density multi-gigabit test fixtures. The large size of an ATE test fixture can require high speed signal routing on the order of 25 to 50 cm (10 to 20 inches) (see Figure 1 left) which drives the need for dielectric materials that can maintain a uniform layer thickness and material over distances even the PCB fabrication process.
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