Optimize Flip Chip Interconnect Design using Designed Experiment Approach with 3D Modeling and Simulations

摘要

Low-k interlayer dielectrics (ILD) have been in volume production for several years. However, a low defect level of ILD delamination beneath the flip chip component bond pad has consistently been reported. Although steps can be taken to eliminate this in current low-k designs, the occurrence rate of this defect can increase as ultralow-k (ULK) materials are introduced for future technology nodes. The flip chip assembly process can create the highest level of mechanical stress for the ILD level. A very cost efficient and timely method for comparing the many variations of package design that influence ILD stress is to use Finite Element Method (FEM) technique. This paper will discuss the use of a 3D Finite Element (FE) simulation study of the flip chip die attach reflow process. It compares the ILD stress of different packaging variables using a factored DOE analysis approach. Variables considered in this report include last metal Cu bond pad design, redistribution layer pad dimensions, passivation specifications, die size, die thickness, and substrate thickness. A comparative methodology will be applied to the simulated results to rank each variable with respect to influence on ILD stress during the flip chip die attach reflow process.