Die thickness of common, high-volume chip stacks range between 50-100μm while thinning industry aims towards ultrathin chips of 10μm thickness or even below. For the first time, the required interconnect length between vertically arranged adjacent chip layers has therewith reached dimensions, that can be reasonably realized by anisotropic conductive adhesives layers (ACA). Accordingly, a three dimensional arrangement by alternate stacking of ultra thin flip chips and interposers using anisotropic conductive adhesive bonding technology is within the bounds of possibility, such that the conductive particles are forming the vertical interconnects between the chip-interposer layers. Based upon such assembly concept prototypes have been made within a first laboratory scale feasibility study. In combination with polyimide thin film interposers, ultrathin low pin count ACA bonded test chips with 4-Point-Kelvin- and Daisy-Chainstructures have been used to build a 4-layer flip chip stack with a thickness of approximately 170μm without encapsulation. First electrical measurements have shown promising results. The reduction to basically one bonding technology to realize the chip-interposer- and the interposer-interposer connections is one of the main benefits with a certain low-cost potential. On the other hand, issues as limited chip/package area ratio, the demand for ultrathin chips with manifold challenges and upcoming detailed electrical characterization of such chip stacks have to be considered. Pros and cons are openly discussed. Special attraction is provided by applying and combining basically known packaging technologies to obtain an innovative but somehow simple 3D flip chip assembly with certain future application potential.
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