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Novel Variation-Aware Circuit Design of Scaled LTPS TFT for Ultra low Power, Low-Cost Applications

机译:用于超低功耗,低成本应用的缩放LTPS TFT的新型变异感知电路设计

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Recently, the demand for ultra low-power and low-cost digital design has grown significantly due to the fast growth of battery-operated portable applications. Many such applications need circuits to be fabricated on flexible substrate such as polymer, glass etc. Low Temperature Polycrystalline Silicon Thin Film Transistors (LTPS-TFTs) have been a promising candidate to realize digital circuits on such flexible substrates with low manufacturing cost. Typically, TFT device sizes are large with many high defect Grain Boundary (GB) regions in the channel. Therefore, they usually operate at high supply (10~20V) to achieve sufficient current drive ability. Device optimization (i.e, scaling of L, Tox etc) can allow us to reduce the supply voltage for low-power and better performance but that would increase the statistical variations induced by randomly located GBs. Due to polycrystalline material properties, this inherent GB variation is much more significant than the other parametric variations (i.e., L, W and Tox variation). To ensure low power dissipation, good performance and robustness, it is imperative to develop techniques which can predict and minimize the effect of such variations in the circuits. In this work, we explore an efficient design methodology to aggressively reduce the device-to-device variation in LTPS-TFT circuits. First, a Response Surface Method (RSM) is used to accurately predict the statistical variation in LTPS-TFT devices. Our simulation results in 200nm technology node show that due to the intrinsic variation induced by the random position and orientation of Grain Boundaries (GBs) in the channel, 61% variation (σ/μ) in I{sub}(ON) can be observed. Under this assumption, we propose a variation-aware circuit design technique based on the Multi-Finger Parallel (MFP) TFT structure. It is shown that by using our proposed MFP TFT structure, one can reduce the variation (σ/μ) in I{sub}(ON) by 18%~30% with 9%~27% overhead in area.
机译:最近,由于电池供电的便携式应用的快速增长,对超低功耗和低成本数字设计的需求显着增加。许多这样的应用需要在柔性基板上制造电路,例如聚合物,玻璃等低温多晶硅薄膜晶体管(LTPS-TFT)是实现在具有低制造成本上的这种柔性基板上的数字电路的有希望的候选者。通常,TFT器件尺寸大,并且在通道中具有许多高缺陷晶界(GB)区域。因此,它们通常在高电源(10〜20V)下运行,以实现足够的电流驱动能力。设备优化(即L,TOX等的缩放)可以允许我们降低低功耗和更好性能的电源电压,但这会增加由随机位于GBS引起的统计变化。由于多晶的材料特性,这种固有的GB变化比其他参数变化更大(即,L,W和TOX变化)要大得多。为确保低功耗,良好的性能和鲁棒性,因此必须开发能够预测和最小化电路这种变化的技术的技术。在这项工作中,我们探讨了高效的设计方法,以积极降低LTPS-TFT电路的设备到设备变化。首先,使用响应面方法(RSM)来准确地预测LTPS-TFT设备的统计变化。我们的仿真结果在200nm技术节点中显示,由于在通道中的晶粒边界(GBS)的随机位置和取向引起的内在变化,可以观察到I {sub}(上)中的61%变化(σ/μ) 。在这种假设下,我们提出了一种基于多指平行(MFP)TFT结构的变形感知电路设计技术。结果表明,通过使用我们所提出的MFP TFT结构,可以将I {sub}(上)中的变化(σ/μ)降低18%〜30%,在区域中具有9%〜27%的开销。

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