All-Optical and Optoelectronic Serial-to-Parallel Conversion of High-Speed, Asynchronous Optical Packets

摘要

In recent years, research on optical packet-switched (OPS) networks has received considerable attention with its potential to maximize throughput, scalability, and flexibility [1]-[5]. On the other hand, the realization of an OPS network faces severe technical challenges, as various packet-processing functions (label swapping/processing, buffering) must be performed on high-speed asynchronous burst input optical packets, on a packet-by-packet basis, at each node of the network. In conventional electrical routers, electrical demultiplexer and clock recovery circuits resolve the mismatch between the optical data rate and the speed of current Silicon-CMOS technology, thus allowing the application of CMOS circuits for signal processing and buffering. However, these interface circuits are ill-suited for the burst mode operation required for an asynchronous input, consume large amounts of power, and may be insufficient in terms of speed. As an alternative, OPS nodes that incorporate all-optical signal processing techniques for label processing and/or all-optical buffering with fiber delay lines have been proposed, but these approaches often lack functionality and scalability, and require complicated control schemes. These difficulties encountered by all-electrical and all-optical approaches perhaps lend credence to a hybrid approach, which would leverage CMOS density and functionality for the signal processing and buffering tasks while implementing optical and/or optoelectronic devices as the interface which performs the necessary serial-to-parallel conversion (SPC) of the high-speed asynchronous input optical packets. Proposals for SPC have included a time-to-wavelength mapping technique that utilizes wavelength conversion [6], and time-to-space mapping techniques based on four-wave mixing in a surface-normal optical switch and second harmonic generation in a waveguide device [7], [8]. However, these schemes may be difficult to scale to higher capacity and suffer from poor switching efficiency. In this paper, we review two approaches for SPC of asynchronous burst preamble-free optical packets which alleviate these issues in a compact, low-power form. The first is an optoelectronic approach targeted for 10-Gb/s to >40-Gb/s packets, based on an optically clocked transistor array (OCTA). SPC and parallel-to-serial conversion (PSC) (i.e., multiplexing), as well as generation of the clock required for both conversion functions, are achieved with a single, low-power OEIC chip [9]. The second is an all-optical approach that employs optical switching by means of differential spin excitation, for SPC of 40-Gb/s to 1-Tb/s optical packets [10]. Combined with CMOS, these interfaces enable a high-performance, highly scalable approach to optical packet switching.