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Joint Timing Recovery and Data Detection for High Density Perpendicular Recording

机译:高密度垂直记录的联合时序恢复和数据检测

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Joint maximum-likelihood (ML) estimation of sampling phase error and data sequence allows timing recovery at low channel signal-to-noise ratios (SNRs). In per-survivor timing recovery of [1], joint ML estimation is done by generating a sampling phase error estimate for each branch in the Viterbi trellis using the local bit sequence implied in the given branch and readjusting the sampling position of the read signal for that branch for the next symbol cycle. The scheme effectively runs a separate parallel phase locked loop (PLL) as well as a sampling device for each of the branches in the trellis. In the phase-estimating maximum likelihood scheme of [2], on the other hand, phase estimation is also performed for each branch separately, but a delayed phase estimate common to all survivor paths is released to a global low pass filter whose output drives a voltage controlled oscillator (VCO) that in turn controls the sampling time of a single analog-to-digital converter (ADC). Thus, there exist parallel phase estimates incorporated into the Viterbi trellis branch metric computation but only one global PLL exists effectively. The phase error detector of [2] is also different from that of [1] in that [2] is based on maximizing the conditional probability density function of the overall error accumulated over a certain time window, given the phase offset, whereas [1] chooses the derivative of the accumulated error as the timing function.
机译:取样的相位误差和数据序列的联合最大似然(ML)估计允许在低信道信号噪声比(SNR)的定时恢复。在每幸存者定时恢复[1],关节ML估计是通过使用在给定的分支所隐含的本地的位序列生成用于在维特比网格中的每分支的采样相位误差估计,调整所述读取信号的该取样位置完成该分支下一个符号周期。该方案有效地运行一个分开的平行的锁相环(PLL)以及用于在每一个网格的分支的取样装置。在的相位估计最大似然方案[2],在另一方面,还为每个分支执行相位估计分开,但是延迟的相位估计共同所有幸存路径被释放到其输出驱动一个全局低通滤波器电压控制振荡器(VCO),其反过来控制单一模拟 - 数字转换器(ADC)的采样时间。因此,存在并入维特比分支度量计算并行阶段的估计,但只有一个全局PLL有效存在。 [2]的相位误差检测器也从[1]在[2]是基于最大化积累在特定时间窗口中的总误差的条件概率密度函数,给定的相位偏移,而[1不同]选择累积误差作为定时函数的导数。

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