This paper evaluates the behavioral effect of RObust Header Compression (ROHC) and packet aggregation in multi-hop wireless mesh networks. ROHC itself shows around 20% achieved rate improvement on a line of wireless link even if as the number of mesh router increases, total achieved rate gradually decreases. Packet aggregation cooperating with ROHC provides 4 to 10 times achieved rate improvement and results in maximum 6 times reduction of end-to-end delay. Even if the ROHC and packet aggregation gives such a promising improvement, we need to identify effect of the processing time of the two schemes on overall wireless mesh network behaviors. To do this work, we measure/use ROHC processing time from Pentium 4 and RouterBOARD 230, and apply the results into NS-2 simulations. The simulation results show high performance improvement from ROHC and packet aggregation deteriorates as a general purpose processor in a mesh router takes much time to deal with the two schemes. This result motivates a hardware design be required to speed up the processing units of the two schemes. Consequently, we propose a hardware system model for ROHC and packet aggregation by using SystemC Hardware Description Language (HDL). From the SystemC results, we conclude the proposed built-in processor design for the two schemes keeps performance improvement by enhancing the low speed processing power of general purpose processors.
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